1. Field of Use
The present invention relates to cache memory systems and more particularly to cache memory systems shared by a plurality of processing units.
2. Background
The related copending patent application titled, "Multiprocessor Shared Pipeline Cache Memory", discloses a cache memory subsystem which has two pipeline stages shareable by a plurality of sources including a number of independently operated central processing units. The first pipeline stage provides for a directory search and compare operation while the second pipeline stage performs the operations of fetching the requested data from the cache buffer memory and its transfer to the requesting source. Timing and control apparatus couples to the sources and allocates each processing unit, time slots which offset their operations by a pipeline stage. Thus, the processing units operate independently and conflict free.
In sharing a cache memory or main memory between a plurality of processing units, there can occur sequences of events or operations which can give rise to incoherency. To avoid this, one solution is to have the processing units share the available memory space and provide a locking mechanism which would prevent one processing unit from modifying information being accessed by another processing unit. While this solution works well for main memory, it can result in excessive data replacement or trashing which reduces the cache hit ratio. Additionally, this type of arrangement reduces the ability for each processing unit to operate independently.
Accordingly, it is a primary object of the present invention to provide a memory space allocation scheme which maximizes the independent operation of processing units which share a cache memory.
It is a further object of the present invention to maintain coherence in a cache memory system which is shareable by a plurality of independently operating processing units.